1. Field of the Invention
The present invention relates to the field of data communication. More specifically, the present invention relates to automatic data sampling timing adjustment, and its application to reducing data transmission errors.
2. Background Information
Advances in integrated circuit and microprocessor technologies have led to wide spread deployment and adoption of computing devices. Examples of computing devices include servers, personal computers and “special” purpose computing devices. Personal computers may have form factors, such as desktop, laptop, tablet, and so forth. “Special” purpose computing devices may include personal digital assistants (PDA), wireless mobile phones and so forth.
Concurrently, advances in networking, telecommunication, satellite and other related technologies have also led to increase connectivity between the various computing devices. Numerous applications and computing needs involve accessing, retrieving and exchanging data between computing devices interconnected over local and/or wide area networks. The networking connections may be wire based or wireless, or both (on different portions of the connections). The networks may be private and/or public.
To accommodate the larger and larger volume of data that need to be exchanged, data transmission rates/speeds, whether it is within a single integrated circuit, a circuit board, between two local devices or over a long distance networking/telecommunication connection, have steadily increased over the years.
Due to noise, signal jitters, as well as other factors, not all data transmitted will be received properly. That is, the data signals may not be presented or may be corrupted at the time periods when they are supposed to be read (also referred to as sampled). The result is data transmission error. The likelihood of an error condition occurring increases, as data are transmitted in parallel, or as operating speed increases (with the margin of tolerance decreasing correspondingly), or both.
For example, when data are transmitted between a link layer device and a physical layer device in accordance with the Optical Internetworking Forum's System Packet Interface Level 4 Phase 2 (OIF-SPI4-02.0), 16 bits are transmitted on the “data path” in parallel at a frequency as high as 644.53 MHz (for 10G Ethernet applications). As a result, the likelihood of an error condition occurring is substantially higher.
Most data transmission protocols, whether the transmissions are made over a private connection, a shared bus, a local/wide area networking connection, typically do include some error detection and handling/correction procedures. For examples, parity bits and/or cyclic redundancy checks (CRC) may be employed for error detection and/or correction. However, these prior art error detection and correction techniques, while necessary and provide for smooth or even transparent recovery, have a tendency of reducing and/or impacting the overall operational efficiency.
Thus, it is desirable if occurrence of data transmission errors can be reduced, especially in high speed or high performance data communication.